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Espressif Systems /ESP32-C6 /HINF /CFG_TIMING

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Interpret as CFG_TIMING

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0NCRC0PST_END_CMD_LOW_VALUE 0PST_END_DATA_LOW_VALUE 0SDCLK_STOP_THRES0SAMPLE_CLK_DIVIDER

Description

Timing configuration registers

Fields

NCRC

configure Ncrc parameter in sdr50/104 mode, no more than 6.
PST_END_CMD_LOW_VALUE

configure cycles to lower cmd after voltage is changed to 1.8V.
PST_END_DATA_LOW_VALUE

configure cycles to lower data after voltage is changed to 1.8V.
SDCLK_STOP_THRES

Configure the number of cycles of module clk to judge sdclk has stopped
SAMPLE_CLK_DIVIDER

module clk divider to sample sdclk

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data